The present invention relates to an insulated-gate field-effect transistor integrated delay circuit for digital signals. More specifically the invention pertains to such a delay circuit whereby a delay adjustable in n equi-distant steps can be produced using 2n cascaded static inverters each consisting of a switching transistor and a load transistor. An odd-numbered inverter and the following even-numbered inverter form one of at least n stages giving the delay t and having their outputs coupled to the delay output via a 1-out-of-n selector switch. The delay is adjusted and regulated by a digital measuring arrangement with a counter followed by a digital-to-analog converter.
A delay circuit of this kind is disclosed in the published Patent Application EP No. 0 059 802 which corresponds to U.S. patent application No. 349,228, filed Feb. 16, 1982 and which issued as U.S. Pat. No. 4,489,342 on Dec. 18, 1982 and which assigned to the same assignee. In the arrangement shown there in FIG. 1, the stage delay, which otherwise varies because of manufacturing variations, is maintained constant by connecting an odd number of inverters to form a ring during delay intervals ("rest periods") and thus producing an oscillation from whose frequency a control signal is derived. The control signal controls the bias of the load transistors via the digital-to-analog converter in such a way that the stage delay is held constant.
With this arrangement, variations in stage delay due to manufacturing variations can be compensated for only to a limited extent because the pulling range is limited as a result of the influence exerted on the load transistors. The output voltage of the digital-to-analog converter influences the ON resistance of a load transistor via the gate of the latter, and the range of variation of this ON resistance is not sufficient for the intended purpose.